Synthesizing Performance-targeted Analog Layout via Early Subcircuit-level Post-simulation
碩士 === 國立交通大學 === 電子研究所 === 105 === The development of analog IC layout generation remains challenges to IC designers due to the imprecise estimation of circuit performance in advanced technology. However, the previous layout results or templates can be reused for the purpose of closing the simulati...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/hx5j7y |