Study of JL and IM Gate-All-Around Poly-Si Nanowire TFTs as SONOS Memory device

• Main Authors: Chang, Yuan-Hao, 張遠豪
• Other Authors: Sheu, Jeng-Tzong
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/2a9gyk

碩士 === 國立交通大學 === 材料科學與工程學系奈米科技碩博士班 === 105 === Recently, the dimension of device and gate length scaling continuously along with Moore’s Law result to short channel effect (SCE) including drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL) since the gate couldn’t control the channel effectively. In this thesis, we use the poly-Si nanowire (NW) channel encased by gate-all-around (GAA) structure to enhance the gate controllability and suppress the SCE. In this research, the GAA poly-Si NW thin-film transistors(TFTs) device possess excellent transistor transfer characteristics including higher driving current ~〖10〗^(-6) A at low drain voltage 1 V , lower steep subthreshold swing (170±20 mV/dec) , high on/off current ratio ~〖10〗^8 and a virtual absence of DIBL (50±15 mV/V). It shows that the GAA SONOS memory device would improve the characteristics of memory due to the corner effect including excellent programming/erasing (P/E) efficiency that can achieve threshold voltage shift (ΔV_th) of 2 V at 13 V stress and ΔV_th of 1.5 V at -16 V stress in 1 μs. Moreover, the device also have better retention behavior expected to remain ΔV_th of 2 V after 2 years and great endurance characteristics that can program and erase up to 〖10〗^6 repeatedly .