Study of JL and IM Gate-All-Around Poly-Si Nanowire TFTs as SONOS Memory device
碩士 === 國立交通大學 === 材料科學與工程學系奈米科技碩博士班 === 105 === Recently, the dimension of device and gate length scaling continuously along with Moore’s Law result to short channel effect (SCE) including drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL) since the gate couldn’t control the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2a9gyk |