Analysis on Hot Carrier Reliability for High Voltage MOS Device with Different Processes

• Main Authors: Chun-YenChen, 陳俊諺
• Other Authors: Jone-Fang Chen
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/jcnnfq

碩士 === 國立成功大學 === 微電子工程研究所 === 105 === In this thesis, we investigated devices is High Voltage MOSFETs (HV-MOSFETs), and analysis hot carrier reliability for different Si recess depth. In our study, we have HV-MOSFETs with three different Si recess depth. The deepest to the shallowest range is about 15 nm. First, we introduced the structure of HV-MOSFETs, its advantage and disadvantage. Moreover, hot carrier effect mechanism and reduce hot carrier effect methods were be introduced. Then we introduced the measurement method and the setting of bias condition in this thesis, and explained the formation reason of Si recess structure. We will present the measurement results for ID-VG, ID-VD and ISUB-VG in terms of the basic electrical characteristics of the HV-MOSFETs. The main contents of this thesis are the study of substrate current for the amount of hot carrier degradation. Based on the unexpected results of our experimental measurements, this device with a Si recess structure has an abnormal hot carrier degradation. In general, the larger substrate current, the device hot carrier degradation should also be larger. However, we measured the degradation trend is that the larger substrate current induced hot carrier degradation is smaller. For the abnormal degradation, we analysis of experimental data and computer-aided simulation (TCAD) software, we can find that the substrate current caused by the larger part of the reason is its internal electric field and impact ionization rate is larger. However, we have purposed three reasons to explain this abnormal phenomenon. First, a deeper Si recess depth is caused by excessive etching induced more defects where below spacer. Secondly, the topology difference induced this phenomenon. Thirdly, the linear region drain current of a deeper Si recess depth is closer to interface (Si/SiO2) than shallower Si recess depth. Therefore, the current path of a deeper Si recess device is affected by interface state more than shallower Si recess device. So a deeper Si recess device has more degradation than shallower Si recess device. According to our measurement data and simulation results, it can be found that Si recess has little effect on the basic electrical performance of devices, but this structure is not ignore issue in hot carrier reliability. Because the depth of Si recess increases, the amount of hot carrier degradation of the device is increases. Therefore, it is an important challenge to reduce the production of Si recess structure in the process of device.