Design and Implementation of 1.25-5.84 Gb/s Reference-Less 1/4-Rate Clock and Data Recovery Circuit for M-PHY Application
碩士 === 國立中興大學 === 電機工程學系所 === 105 === There is growing interest in the use of 3C applications for high-speed interconnects. According to process evolution, the volume of the data transferring between processor and memory cells is larger and larger. This progress making the conventional data bus can...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/38289823033657280201 |