The Design of High Speed Duty Cycle Corrector Circuitry
碩士 === 逢甲大學 === 電子工程學系 === 105 === This paper presents a high speed duty cycle corrector circuit. The propose circuit is designed in 0.18- m CMOS process and the simulation result to prove the extant of improvement. The duty cycle of the input clock can accept between 10% to 90%, corrector the duty...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8awdfc |