| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 105 === As the process technology continues to shrink, the size of a standard cell is smaller. Thus, the design complexity is higher. Moreover, the influence of on-chip variation also becomes more serious. Especially, in the clock tree synthesis, a small timing variation may make a big impact on the chip. Therefore, the reduction of the on-chip variation of clock tree is an important topic for the industry.
A system-on-chip design consists of a lot of blocks. Top-level clock tree among blocks is much easier influenced by on-chip variation because the distance between blocks is longer. If we can reduce on-chip variation of top-level clock tree effectively, the on-chip variation of the whole chip is easier to control.
Base on this observation, in this thesis, we propose a design flow, which can be integrated with existing APR Tools, for top-level clock tree design. The proposed design flow is below. First, we analyze the original clock tree which is synthesized by APR Tools. Then, we develop an algorithm to find the new location of each clock buffer and guide the APR tool to resynthesize the top-level clock tree. Experimental results show that, after our optimization, we can obtain a top-level clock tree with a significantly reduced on-chip variation
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