On-Chip-Variation-Aware Top-Level Clock Tree Synthesis Methodology
碩士 === 中原大學 === 電子工程研究所 === 105 === As the process technology continues to shrink, the size of a standard cell is smaller. Thus, the design complexity is higher. Moreover, the influence of on-chip variation also becomes more serious. Especially, in the clock tree synthesis, a small timing variation...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/27932634259051444038 |