Spur Reduction of 1.5GHz Frequency Synthesizer by using Delay-locked Loop techniques

• Main Authors: Chia-hui Lin, 林家慧
• Other Authors: Ming‐Lang Lin
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/23703987675070232038

碩士 === 大同大學 === 電機工程學系(所) === 104 === In suppressing reference spurs, both the current mismatch improvement of charge pump and the periodicity of reference signals disarragement are usually used to reduce reference spurs. Therefore, The delay locked loop(DLL) techniques is adopted in this thesis.The period of the reference signal and feedback signal divided seven parts by DLL. The reference signal with seven different phase with be chosen by pseudo-random binary sequence(PRBS).It uses the method of random to upset the output signals UP and DOWN of PFD to reduce the reference of spurs. When the system has not been locked, it operates in the traditional frequency synthesizer mode. When the system is approaching being locked, the pseudo-random binary sequence circuit randomly selects one of the seven group of reference signals and feedback signals to make the reference spurs move to the high frequency. TSMC 0.18 µm technology is used in the thesis, where the reference signal’s frequency is 23.5MHz, and the output frequency is 1.5GHz. The reference spurs can be reduced from -28.341dBw to -38.581dbw Keyword: reference spurs, PRBS, Charge-pump