A DIGITALLY CALIBRATED 11-BIT 10-MS/s SAR ADC WITH MONOTONIC SWITCHING SPLIT CAPACITOR ARRAY

• Main Authors: Wei Tung, 童偉
• Other Authors: Huang, Shu-Chuan
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/89282578310273443460

碩士 === 大同大學 === 電機工程學系(所) === 104 === In this thesis, a digitally calibrated 11 bit 10MS/s asynchronous differential SAR ADC is presented. A monotonic capacitor switching procedure is used in the design, such that the input pair of the comparator converges to the ground. In this structure, the differential inputs are sample to the input pair of the comparator, where the MSB can be determined without using MSB capacitor. In order to further reduce the area, this design uses split capacitor structure, which affects the linearity of the system. A digital calibration method is proposed to minimize the effects including capacitor mismatch and the bridge parasitic capacitor. The SAR ADC is implemented with a 0.18um CMOS technology. At a 1.8-V supply and 10 MS/s, the ADC achieves an SNDR of 65.2 dB and consumes 0.62 mW, resulting in a figure of merit (FOM) of 21 fJ/conversion-step. The ADC core occupies an active area of 350m  350m.