Pattern Engineering in Smart-cut SOI before Bonding for Power MOSFET
碩士 === 東海大學 === 電機工程學系 === 104 === In this paper we propose a structure to improve the breakdown voltage and unify the electric field of a SOI LDMOSFET. The buried oxide layer of SOI wafers is patterning designed to change the dielectric material positions to adjust the electric field distribution...
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| Format: | Others |
| Language: | zh-TW |
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2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93939585025234667210 |
| Summary: | 碩士 === 東海大學 === 電機工程學系 === 104 === In this paper we propose a structure to improve the breakdown voltage and unify the electric field of a SOI LDMOSFET. The buried oxide layer of SOI wafers is patterning designed to change the dielectric material positions to adjust the electric field distribution in the drift areas. We use Smart-Cut SOI technology as the base; and apply the pattern engineering to etch the oxide layer before wafer bonding. Such that we are able to introduce an alternating oxide and air layer into a SOI wafer, and produce the ultra-high voltage LDMOSFET above 600V on this wafer. We used TCAD to simulate the device. Due to the enhanced dielectric layer electric field (ENDIF) in oxide and air junction in the buried oxide, the electric field distribution in the silicon epi-layer is changed accordingly. By making multiple intersections of oxide and air the electric field distribution is more uniform and higher breakdown voltage than buried air gap structure (BAGS) is obtained. The device length is then shortened to reduce the turn-on resistance and still keep the identical breakdown voltage.
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