| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === A high accuracy FPGA Vernier time-to-digital converter based on PLL delay matrix is presented. Previously, a FPGA Vernier TDC was proposed to achieve 2.5 ps bin size and -2.98~ 3.23 LSB integral nonlinearity (INL) [1]. However, the cell delays of the delay lines cannot be fully controlled and thus the TDC performance is strongly dependent on the stochastic distribution of the cell delays. Moreover, the input range is limited to be less than 20ns. In this thesis, a high accuracy FPGA Vernier time-to-digital converter (TDC) is realized with PLL delay matrix instead to get rid of the impact of possible PVT variations.
The proposed TDC is aimed to provide a PVT-insensitive solution with both high resolution and wide measurement range. The delay of all cells is under the precise control of major and minor PLLs. Utilizing the concept of delay wrapping, the PLL phases are distributed evenly within the reference period to achieve an extremely fine resolution. To reduce the impact of temperature-sensitive offset, a cancellation circuit is adopted to substantially reduce the offset and confine the output difference to within merely 5 LSB. Experimental results achieve a PVT-insensitive TDC resolution of 1ps. The long-term integral nonlinearity (INL) is measured to be merely -2.471 ~ 2.578 LSB and the corresponding differential nonlinearity (DNL) is -2.969 ~ 2.813 LSB. This TDC was tested to be fully functional over 0C to 50C ambient temperature range with very low resolution variation. Its performance is even superior to many full-custom TDC designs.
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