A High Accuracy FPGA Vernier Time-to-Digital Converter Based on PLL Delay Matrix
碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === A high accuracy FPGA Vernier time-to-digital converter based on PLL delay matrix is presented. Previously, a FPGA Vernier TDC was proposed to achieve 2.5 ps bin size and -2.98~ 3.23 LSB integral nonlinearity (INL) [1]. However, the cell delays of the delay lines...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/sj7kxg |