Design of Received Signal Strength Indicator Circuit in CMOS Process
碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis designs received signal strength indicator circuits (RSSI) by using successive detection logarithmic amplifier (SDLA) topology under TSMC 0.18μm and 40nm CMOS technology. Successive detection logarithmic amplifier composes of limiting amplifier, unb...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16649281507503132590 |