| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 104 === Delay-Locked-Loop (DLL) is widely used in today’s System on Chip (SoC), DRAM interfaces or other timing circuits. Conventional analog DLLs can achieve better performance in jitter and skew, but nowadays digital DLLs becomes a better choice than analog DLLs. Our previous work in [9] proposed an ADPLL compiler for the use in timing-related circuit designs and has been widely used. In this work, we proposed a cell-based architecture of delay line for our all-digital DLL (ADDLL) circuit, which can provide small resolution and wide tuning range to meet the user’s demand. Moreover, we propose an ADDLL compiler which can not only generate an ADDLL circuit more easily and conveniently than a typical manual design, but also support easy process migration, saving a large amount of design effort. The transistor level simulation results show that this compiler can provide single clock frequency operation from 50MHz to 1.25GHz in TSMC90 process and 50MHz to 1GHz in TSMC18 process.
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