Parameterized Cell-Based All-Digital Delay-Locked-Loop (ADDLL) Architecture and Its Compiler to Support Easy Process Migration
碩士 === 國立清華大學 === 電機工程學系 === 104 === Delay-Locked-Loop (DLL) is widely used in today’s System on Chip (SoC), DRAM interfaces or other timing circuits. Conventional analog DLLs can achieve better performance in jitter and skew, but nowadays digital DLLs becomes a better choice than analog DLLs. Our p...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29359072262319556631 |