Compiler and Architecture Support for Affine Register File on GPU

• Main Authors: Kan, Li Chen, 甘禮禎
• Other Authors: Lee, Jenq Kuen
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/tz9wbf

碩士 === 國立清華大學 === 資訊工程學系 === 104 === Graphic Processing Units (GPUs) are designed with a large number of threads to achieve high throughput and performance improvement. For rapidly switching to a different task, each thread has its own registers to store its context. These numerous register files play an important role in performance improvement, but it also takes up a key part of GPU power consumption. Moreover, as shown in previous works, single instruction, multiple threads (SIMT) execution model used in modern GPUs exhibits significant computation redundancy. They execute the same input values and generate the same output values. To eliminate these redundancy computations, scalar/uniform register architecture of GPU is proposed. In this thesis, we proposed the affine register file design which deals with not only the uniform vectors but also the affine vectors. We dispose two registers to store two scalar values, base and stride, of the affine vectors and specific affine ALU to execute the affine computation. Compiler analyzes the value type which is uniform, affine or a general vector and allocates register according to energy saving and performance consideration. In the experiment, it shows that our design can reduce 72.98% and 77.88% energy consumption of register file and ALUs respectively and average 5.25% of total energy consumption of GPU.