| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 104 === As technology advances, the interconnect delay gradually dominates the circuit performance but the emerging issues makes timing optimization become more complicated. Since 32nm nodes, different tiers of layers have different default wire widths such that the layer assignment of routing wires greatly impacts interconnect delay. Moreover, below 16nm nodes, because the wire coupling impacts delay more significantly and wire width cannot be arbitrarily sized to reduce wire capacitance, the timing optimization problem is harder to resolve. This thesis addresses a delay-driven layer assignment problem with consideration of via delay and coupling effect in the global routing stage. A look-up table method is proposed to estimate the coupling capacitance modeled by a probabilistic approach. In order to consider routability, a negotiation-based framework is presented to strike a good balance between delay, congestion, and via count. Finally, the proposed algorithm is able to use parallel wires and non-default-rule (NDR) wires to pursue better delay reduction instead of using wire sizing. The effectiveness of our layer assignment algorithm is well supported by extensive experimental results.
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