Delay-driven Layer Assignment for Sub-16nm Technology Nodes
碩士 === 國立清華大學 === 資訊工程學系 === 104 === As technology advances, the interconnect delay gradually dominates the circuit performance but the emerging issues makes timing optimization become more complicated. Since 32nm nodes, different tiers of layers have different default wire widths such that the laye...
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| Format: | Others |
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2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33664868921084002217 |