| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 104 === Static timing analysis is generally employed to verify the timing of a circuit. To effectively consider on-chip variations, early-late split mechanism is performed commonly. However, this split mechanism introduces unnecessary pessimism, which can mislead timing tests. Common path pessimism removal (CPPR) attempts to eliminate such pessimism by tracing those potentially problematic paths and correcting the timing information for those paths. During an optimization flow, a circuit could be modified by lots of operations and consequently the timing information has potential to be significantly affected. To keep timing information consistent for ensuring the timing closure, quickly and accurately updating timing information becomes a crucial issue.
In this thesis, we propose a modified timing graph to avoid the existing CPPR algorithm proposed in [3] from suffering the extra penalties caused by rise/fall transitions spilt. Furthermore, we propose an incremental timing framework which is friendly on handling a large number of circuit modification operations. We make effort to promote the accuracy with saving runtime and memory usage. Experimental results show that our timer can outperform the winners of TAU 2015 contest by (1)1.58X speedup over iTimerC 2.0 and 2.21X speedup over UI-Timer 2.0, (2) accuracy improvement and (3) much less memory usage.
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