Incremental Timing Analysis with Common Path Pessimism Removal
碩士 === 國立清華大學 === 資訊工程學系 === 104 === Static timing analysis is generally employed to verify the timing of a circuit. To effectively consider on-chip variations, early-late split mechanism is performed commonly. However, this split mechanism introduces unnecessary pessimism, which can mislead timing...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81562879110942237996 |