A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches
碩士 === 國立中山大學 === 資訊工程學系研究所 === 104 === We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor, error detection code or error correction code for memory)...
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/838rm6 |
| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 104 === We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor, error detection code or error correction code for memory) and automatically generates configuration file for RTL code. In addition, the application can be encoded by our Analyzer and generate signature augmented program to detect the control-flow error in the run-time. In the end, it also performs simulation-based fault injection campaign to evaluate the fault detection capabilities of different fault-tolerant configurations. The IDE and GUI have been implemented for Andes N801s microprocessor core. This workbench would also provide estimated performance, cost overheads and fault coverage for the generated fault-tolerant architecture in order to suite different safety level applications or user requirements.
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