Zero-Latency Cluster-Error Correction and Reliability Analyses for TSVs in 3D ICs
碩士 === 國立彰化師範大學 === 電子工程學系 === 104 === In order to extend Moore's Law, three-dimensional stacked integrated circuits (3D-IC) has been seen as a new solution. However, the yield of 3D-IC base on through silicon via(TSV) is still now high. Therefore, TSVs testing and repair methods has become an...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77334474475211950617 |