Refining The Package Processing and Material Analysis for Wafer Level Chip Scale Package
碩士 === 國立交通大學 === 理學院應用科技學程 === 104 === Wafer level package is one of the advanced integrated circuit (IC) packages.The packaging processing is carried out directly on the whole wafer after it is produced. Then, the packed wafer is cut into single ICs. Neither wire bonding nor fillers are required i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/42722700973187991870 |