Characteristic Simulation of Next-Generation InGaAs Multiple-Gate MOSFET Devices

• Main Authors: Huang, Cheng-Hao, 黃政皓
• Other Authors: Li, Yiming
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/53725871392149093197

碩士 === 國立交通大學 === 電信工程研究所 === 104 === The semiconductor industry has developed fast for the past decades. To maintain the advancement of Moore’s law, innovations of fabrication process, device structures with vertical channel, and high-mobility materials play the significant roles on the complementary metal-oxide-semiconductor technology scaling. Nowadays, the technology node has extended to 16 nm, sometimes called 14 or 15 nm, and multiple-gate field effect transistors and III-V semiconductors are promising researches, such as InGaAs multiple-gate metal-oxide-semiconductor field effect transistor (MOSFET) device. However, the device simulation and analysis of characteristic fluctuation of optimal InGaAs multiple-gate MOSFETs have not been completely studied. In thesis, we firstly use an experimentally calibrated 3D quantum mechanically corrected device simulation to examine the electrical characteristics with respect to variations of channel fin width (Wfin) and fin height (Hfin) on InGaAs triple-gate MOSFETs. By considering the transfer and output curves, channel quantum confinements, short-channel effects (SCEs), and device manufacture ability, simultaneously, we find that the studied device with Wfin = 10 nm and Hfin varying between 11 and 17 nm has the satisfied characteristics. After that, a channel capping layer of In1−xGaxAs above In0.53Ga0.47As channel layer is further explored. Notably, the conduction band energy of capping layer varied with mole fraction is lower than that of channel layer. By considering the specification to be achieved, like on-/off-state current ratio (ION/IOFF) > 1.7 × 10^6 , subthreshold swing (SS) < 72 mV/dec, and drain-induced barrier lowering (DIBL) < 55 mV/V, we find that the aforementioned device with a 4-nm-thick In0.68Ga0.32As capping layer can provide optimal characteristics for InGaAs trigate MOSFETs. Owing to fabrication limits, rectangular channel may not always guarantee and NiSi-random-metal-grain-induced variability is getting considerable with device scaling. To suppress the fluctuation, the averaged grain size should be smaller than 16 nm^2 and the channel fin angle could be between 85◦ and 90◦, and the fluctuations of threshold voltage (Vth) and SCE parameters are less than 7%. Comparing with recent researches, we have achieved the larger ION/IOFF, the higher cut-off frequency of 282 GHz, and the lower characteristic fluctuations. Secondly, the impact of characteristic variation induced by TiN random work function fluctuation (WKF) on 14-nm gate-all-around nanowire (GAA NW) MOSFETs is examined, and GAA NW MOSFET is compared with bulk FinFET. Under the same Vth of 160 mV, the current ratio (2.37×10^-5/2.47×10^−9) of n-type InGaAs GAA NW MOSFET is 3.5 times higher than that of InGaAs bulk FinFET. They have the similar SS, but the DIBL is decreased by about 30% to 37 mV/V owing to the less influence of drain voltage modulation on electric field of depletion region for GAA NW MOSFET. Although InGaAs has the higher electron mobility, the structure of device channel dominates the gate capacitance. Hence, after normalizing by the effective channel width, InGaAs GAA NW MOSFET has the largest ION of 7.54×10^−4 A/µm, followed by silicon GAA NW MOSFET, and silicon bulk FinFET has the smallest ION of 3.53×10^−4 A/µm. Because the conduction band energy of InGaAs is lower than that of silicon, the IOFF of InGaAs devices are at least 7 times larger than that of silicon. The Vth’s fluctuation (σVth) of GAA NW MOSFET induced by WKF is smaller than that of bulk FinFET. As TiN grain size shrinks into 3 nm^2, the decrease trend of σVth is the most obvious for both silicon and InGaAs GAA NW MOSFETs. Unlike planar MOSFETs, the impacts of WKF random location effect on GAA NW MOSFET and bulk FinFET are insignificant due to the stronger gate to channel controllability, carrier quantization, and quantum capacitance effect. InGaAs device has the large standard deviation of ION (σION) owing to high electron velocity and 15%-high velocity variation. In brief, InGaAs devices possess the better immunity of fluctuation than that of silicon devices in the linear region because of the energy degeneracy effect of materials, where the electron density is less sensitive to the local change of surface potentials. Besides, the σION of GAA NW MOSFET is lower than that of bulk FinFET due to the nature of gate-all-around channel. In summary, this thesis has investigated the device design, simulation, and analysis of InGaAs multiple-gate MOSFET devices and has indicated the proper device settings for optimizing device characteristics. The results can be a useful reference for semiconductor industry as developing the integrated circuit device technology for the next generation.