Numerical Simulation of Program/Erase/Retention in Planar and GAA SONOS with Different Dielectrics
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === In this thesis, we developed a complete and consistent program/erase/retention model which can evaluate the performance boosted by changing structure and dielectrics. According to our model, the program/erase window can be improved by using Gate-All-Around(...
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2625k4 |
| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === In this thesis, we developed a complete and consistent program/erase/retention model which can evaluate the performance boosted by changing structure and dielectrics. According to our model, the program/erase window can be improved by using Gate-All-Around(GAA)structure, and it can be further improved by using SiON as tunneling dielectric. However, usinghigh-k metal gate(HKMG)is the crucial way to improve it. Our modelreproduceserase Vthturn-around behavior, and suggests that reducing gate electron injection contribute to improve it. Retention loss via vertical and lateral direction are also evaluated. It suggests thatusingSiON as tunneling dielectric goes against retention characteristic via vertical direction. The effect of charge lateral migration is evaluated and it is less important to charge vertical loss according to oursimulation result.
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