| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 104 === In this thesis, we present the design of an H.264/AVC Hexagonal Search Motion Estimator IP for a Xilinx Zynq 7020 FPGA platform. The IP will read the chroma subsampling 4:2:0 yuv video data from the DDR SDRAM using the AXI bus protocol, and the hexagonal-based searching pattern is using for block motion estimation. The implementation in this thesis including both software and hardware, and it maintains three reference frames for inter prediction, and the running time of software and hardware will be compared. The IP is implemented by moving the searching area of the block from DDR SDRAM to Block RAM, and when interpolation is needed, the sliding window of the block can be acquired from the Block RAM instead of the DDR SDRAM, and the design reduces data transmission bandwidth significantly. The final design of the Hexagonal Search Motion Estimator IP can be verified using FPGA at 100MHz.
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