Design of a Hexagonal Search Motion Estimator for FPGA
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 104 === In this thesis, we present the design of an H.264/AVC Hexagonal Search Motion Estimator IP for a Xilinx Zynq 7020 FPGA platform. The IP will read the chroma subsampling 4:2:0 yuv video data from the DDR SDRAM using the AXI bus protocol, and the hexagonal-base...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/03714775871041632584 |