A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC with Digital Code Error Correction

• Main Authors: Chia-HsinLee, 李佳欣
• Other Authors: Soon-Jyh Chang
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/64442107517566871093

碩士 === 國立成功大學 === 電機工程學系 === 104 === This thesis presents a single-channel 2.5-bit/cycle 10-bit 160-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with the conventional 2.5-bit/cycle SAR ADC, the proposed input level shifting technique saves one sub-digital-to-analog converter (sub-DAC) and relaxes the requirement on resolution for the other sub-DACs. In addition, the proposed digital code error correction provides a wider error tolerance range by a compact digital design. The proposed ADC was fabricated in TSMC 90-nm CMOS standard 1P9M process, and occupies 262.8 μm × 420 μm active area. At 1-V supply and 160-MS/s sampling rate, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.23 dB. The resultant effective number of bits is 8.55 bits with power consumption of 1.97 mW. The figure-of-merit (FoM) is 32.9 fJ/conversion-step.