A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC with Digital Code Error Correction
碩士 === 國立成功大學 === 電機工程學系 === 104 === This thesis presents a single-channel 2.5-bit/cycle 10-bit 160-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with the conventional 2.5-bit/cycle SAR ADC, the proposed input level shifting technique saves one sub-dig...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64442107517566871093 |