An Improved Successive-Approximation Analog-to-Digital Converter with Offset Calibration Technique
碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 104 === The thesis proposes the design of a 6-bit 100-MS/s improved successive-approximation analog-to-digital converter (ISA-ADC). In this thesis, the improved successive-approximation analog-to-digital converter uses R-2R ladder architecture and includes offset c...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2vnafm |