Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application
碩士 === 逢甲大學 === 通訊工程學系 === 104
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| Format: | Others |
| Language: | zh-TW |
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2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95174111429025297301 |
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ndltd-TW-104FCU05650018 |
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ndltd-TW-104FCU056500182017-08-20T04:07:35Z http://ndltd.ncl.edu.tw/handle/95174111429025297301 Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application 晶片及電路板層級之暫態傳導干擾與大電流干擾耦合路徑之分析 呂政儀 碩士 逢甲大學 通訊工程學系 104 林漢年 2016 學位論文 ; thesis 90 zh-TW |
| collection |
NDLTD |
| language |
zh-TW |
| format |
Others
|
| sources |
NDLTD |
| description |
碩士 === 逢甲大學 === 通訊工程學系 === 104 |
| author2 |
林漢年 |
| author_facet |
林漢年 呂政儀 |
| author |
呂政儀 |
| spellingShingle |
呂政儀 Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application |
| author_sort |
呂政儀 |
| title |
Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application |
| title_short |
Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application |
| title_full |
Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application |
| title_fullStr |
Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application |
| title_full_unstemmed |
Analysis of Conducted Transient Noise Immunity and BCI Coupling Path for Chip and Board Level Application |
| title_sort |
analysis of conducted transient noise immunity and bci coupling path for chip and board level application |
| publishDate |
2016 |
| url |
http://ndltd.ncl.edu.tw/handle/95174111429025297301 |
| work_keys_str_mv |
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