On-Chip All-Digital Low-Power High Resolution Jitter Measurement Circuit with High Variation-Tolerant Working on 1GHz to 3GHz

• Main Authors: LIN WEI-LING, 林瑋玲
• Other Authors: WANG JINN-SHYAN
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/61973217222778364682

碩士 === 國立中正大學 === 電機工程研究所 === 104 === System on chip has been a major development of the VLSI circuit. When many different circuits into a chip, the timing between circuits and circuits must be controlled accurately. PLL circuit is used to generate the source clock in the SoC system. If the clock jitter of the PLL circuit become too much, the mistakes of system operation will be generated. But it is difficult to measure the output clock jitter of the PLL circuit accurately by using external measuring equipments. It not only need to take the high cost of equipment but also the noise may cause that the measured result is not true to the original. For all these reasons, the built-in jitter measurement is be produced. The features of the On-Chip All-Digital High Resolution Jitter Measurement Circuit with High Variation-Tolerant working on 1GHz to 3GHz are high application, high-resolution, process variation, low power and without reference clock. This proposed circuit use self-sampling technique to eliminate the requirement of the reference clock and Calibration circuit to promote the process variation tolerance. in addition, this proposed circuit uses the time amplifier circuit to increase the high accuracy. The On-Chip All-Digital Low-Power High Resolution Jitter Measurement Circuit with High Variation-Tolerant working on 1GHz to 3GHz is designed in UMC 28nm process and TSMC 28nm process. The operating frequency range of this proposed circuit is from 1GHz to 3GHz. The total resolution of this proposed circuit is 0.59ps, power consumption is 0.62mW and the area of the chip is 0.0032mm2.