A High-gain High-speed Fully-integrated CMOS Optical Receiver
碩士 === 國立雲林科技大學 === 電子工程系 === 103 === A high-gain high-speed fully-integrated CMOS optical receiver designed in UMC 0.18μm 1P6M CMOS process technology for visible light wireless communications is presented in this thesis. The regulated cascade (RGC) gain stage is adopted before the transimpedance a...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20175329597308832334 |
| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 103 === A high-gain high-speed fully-integrated CMOS optical receiver designed in UMC 0.18μm 1P6M CMOS process technology for visible light wireless communications is presented in this thesis. The regulated cascade (RGC) gain stage is adopted before the transimpedance amplifier (TIA) to reduce the effect of the input photodiode capacitance (CPD). The equalizer (EQ) and the post amplifier (PA) are adopted to increase the bandwidth and gain, respectively. The optical receiver achieves a total transimpedance gain of 124dBΩ and the bandwidth of 3.02GHz in the presence of a 0.5pF photodiode capacitance. The core current is 35.29mA with the power supply voltage of 1.8V. The active area is 457μm × 109μm.
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