| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 103 === In this thesis, a time-to-digital converter (TDC) with fault correction is presented. The architecture of the proposed TDC adopts a successive approximation (SAR) algorithm with redundancy for automatic correction. Despite fault digital codes maybe appear in circuits due to process, voltage, and temperature variation, if the target value locates in the range of the redundancy, the phase difference of the last stage will be less than the value of the least significant bit.
The proposed TDC is implemented in TSMC 0.18µm 1P6M CMOS process. The frequency of reference signal and input signal are 25MHz and 10MHz, respectively. When the phase difference between both reference signal and input signal is 9ns, the phase difference of the last stage of the proposed TDC and its resolution are 23ps and 39ps, respectively. The power consumption of the proposed TDC is 3.07mW @ 1.8V and its core area is 0.118mm2.
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