The Study of Time-to-Digital Converters with Fault Correction
碩士 === 大同大學 === 電機工程學系(所) === 103 === In this thesis, a time-to-digital converter (TDC) with fault correction is presented. The architecture of the proposed TDC adopts a successive approximation (SAR) algorithm with redundancy for automatic correction. Despite fault digital codes maybe appear in cir...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57325722093431737586 |