| Summary: | 碩士 === 國立臺北科技大學 === 電機工程研究所 === 103 === Due to advances in technology, the complexity of the entity of VLSI design also by the number of modules increases with the increasing complexity and complexity floorplan is relatively improved, not only must meet the minimum total area of design, the total length of the shortest wire
Simulated Annealing past some scholars have proposed to solve the problem of floor plan, however, when the increase in the number of modules, SA will take a long computing time. In view of this, this paper proposes &;quot;Multi-level Floorplanning Based on CUDA&;quot; approach, the application &;quot;Simulated Annealing&;quot; and &;quot;Compute Unified Device Architecture&;quot;, may have overcome the problem of efficient floor plan.
In the paper, the proposed a group may effectively reduce methods analog annealed law space out big, and the district described in detail the methods can be said the team sequence synthetic after 4 module into blocks the module, to the use of CUDA Bruce characteristics of the information gets to the GPU can also be further speed up the implementation programs.
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