Multi-level Floorplanning Based on CUDA
碩士 === 國立臺北科技大學 === 電機工程研究所 === 103 === Due to advances in technology, the complexity of the entity of VLSI design also by the number of modules increases with the increasing complexity and complexity floorplan is relatively improved, not only must meet the minimum total area of design, the total le...
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| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/cefc2u |