Multilevel Floorplanning Based on Partially Uncoarsening
碩士 === 國立臺北科技大學 === 電機工程研究所 === 103 === In conventional integrated circuit design process, the result of floorplan will affect the exterior area of the wafer and the winding length. As time progresses, the number of the chip module also increases, resulting in excessive internal circuit wafer, leadi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/j2tmzh |