New Vcm-Based Subranging SAR ADC with Separated Capacitor Switching Technique
碩士 === 國立臺北科技大學 === 電子工程系研究所 === 103 === This paper initially describes the SA algorithm, architecture, different types of DAC and comparator, dynamic and static parameters. Finally, based on the above studies, the first part of this thesis is 10-bit 30MS/s Subranging SAR ADC with Triple Reference V...
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| Online Access: | http://ndltd.ncl.edu.tw/handle/xus5au |
| Summary: | 碩士 === 國立臺北科技大學 === 電子工程系研究所 === 103 === This paper initially describes the SA algorithm, architecture, different types of DAC and comparator, dynamic and static parameters. Finally, based on the above studies, the first part of this thesis is 10-bit 30MS/s Subranging SAR ADC with Triple Reference Voltage Technique. The capacitor array separated into two sections for getting smaller MSB capacitor. The performance of ENOB is 7.88 bits.
The second part of this thesis is 10-bit 20MS/s Separated Capacitor Array with SAR ADC. To decrease size of capacitors and conversion time of every cy-cling bit. The architecture of SR ADC separated into two of sub-SAR-ADCs. The performance of ENOB is 8.86 bits. These chips are fabricated using 0.18-um 1P6M CMOS technology with 1.8 voltage of power supply.
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