Chip Design of an Analog LDPC Decoder with Building in Self-Testing

碩士 === 國立臺北科技大學 === 電子工程系碩士班(碩士在職專班) === 103 === This thesis proposes an analog low-density parity-check (LDPC) with building in self-testing (BIST). It is based on the sum-product algorithm and by checking parity H-matrix to decide iteration termination. A self-testing hardware technique is also pr...

Full description

Bibliographic Details
Main Authors: Shao-Wei Huang, 黃紹瑋
Other Authors: 李文達
Format: Others
Language:zh-TW
Online Access:http://ndltd.ncl.edu.tw/handle/shg27f