| Summary: | 碩士 === 東海大學 === 資訊工程學系 === 103 === In the wafer production process, cost is an important factor. Due to the requirement of experimental or special purpose chips, for a lower cost consideration, multi-specification dice arrangements are needed to generate these chips.
This study proposes a placement and cut algorithm suitable for the dicing plan. Besides the best locations, this study considers the best cut to decrease production cost by decreasing the slicing collision problem in a dicing plan.
A hierarchical algorithm is used for placement and cut algorithm. Firstly, initialize the location for different chips to simplify the input. Secondly, use slicing tree for the arrangement of the chip placement with the minimum cut. A simulated annealing algorithm combined with a vertical and horizontal conflict and coloring theorem are used to optimize the placement and cut for wafer floorplan.
In the cutting conflict decision period of coloring algorithm (used as an objective function of the SA algorithm), two different methods are compared. The first one considers enumeration of the width and height of each chip to decide if they conflict with each other. The other uses the segment tree data structure to decrease the computation time. The second method is expected to outperform the first one in run time.
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