A Color Interference Checking Chip Dicing Plan for Multiple Project Wafer Accelerated by Segment Tree
碩士 === 東海大學 === 資訊工程學系 === 103 === In the wafer production process, cost is an important factor. Due to the requirement of experimental or special purpose chips, for a lower cost consideration, multi-specification dice arrangements are needed to generate these chips. This study proposes a placement...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73705083617757852548 |