20-60V NLDMOS Low on-resistance device with P-top layer based on BCD Process Technology and LIGBT HV Device Design Optimization of 700V Based on SOI Technology
碩士 === 亞洲大學 === 資訊工程學系 === 103
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/huc565 |