Design and Verification of the Built-in Self-test Circuits for the HDL-based Finite State Machines
碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === This thesis is related to the design and verification of BIST (Built-In Self-Test) circuits for HDL-based FSMs (Finite State Machines). The related research work consists of the following four parts: The first part is to introduce the test methods for FSM circu...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68252700606742569062 |