Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === FinFET has become the most popular solution to overcome short channel effects in advanced technology. However, some research show that defect in FinFET causes extra small delay and the defect is difficult to detect by traditional test sets. Sometimes, defect...

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Bibliographic Details
Main Authors: Kuan-Ying Chiang, 江冠穎
Other Authors: Chien-Mo Li
Format: Others
Language:en_US
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/63277729341924543772