TLB-Aware Block Scheduler: Improving GPU Address Translation Performance for HSA Platform
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 103 === Processor vendors have already embraced heterogeneous systems today. A key component is a shared unified address space in order to efficiently utilize system memory as well as obtain the programmability benefits of virtual memory for integrated CPU and GPU arch...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69815680143863531396 |