Fabrication and Analysis of Silicon-Based Vertical-Type Tunneling Field-Effect Transistor

• Main Authors: Juang, He-Kai, 莊賀凱
• Other Authors: Steve S. Chung
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/78454520049893103686

碩士 === 國立臺灣師範大學 === 光電科技研究所 === 103 === Recently, a transistor with tunneling mechanism called Tunnel FET was proposed as the candidate of MOSFET. Compared to MOSFET, TFET has several advantages: (1)TFET is suitable for low power device due to the higher barrier of the reversed p-i-n junction in TFET. (2)The band-to-band tunneling region is about 10nm, so that the transistor can be shrunk down to 20nm gate length. (3)The subthreshold swing of TFET has ability to surmount 60mV/dec of MOSFET’s physical limit by its distinct working principle. (4)The threshold voltage of TFET depends on bending in the small region, but not in the whole channel region, Vt roll-off is much smaller than that of MOSFET while scaling. The major challenge of TFET is the boosting of on current. In this paper, we design a device with vertical tunneling structure for investigating how to enhance the on current of TFET. The analytic results show that we can find two parts of boosting current, the second boosting current is caused by vertical tunneling, we have proved it by band gap diagram of simulation. And the best source concentration is about 1x1019~1x1020cm-3. It can be adjusted to have appropriate threshold voltage and better subthreshold swing in this region. At the same time, we investigate the issue of fabrication by simulation. It shows that the major issue affecting our performance of device is the quality of gate oxide.The bad gate oxide induces trap assist tunneling, then the current of gate will directly tunnel through the gate oxide, and that’s where the leakage current come from.