| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 103 === Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the delay of a TSV non-intrusively by a transition time binning procedure. However, it is not suitable for longer interconnects in an interposer or in the Re-Distribution Layer (RDL) of a WLP-packaged IC, as the cost could become prohibitively high due to large area overhead. To overcome this limitation, we propose a new scheme in this thesis by incorporating a Distributed Time-to-Digital Converter (d-TDC). Experimental results indicate that such a scheme can support on-line delay monitoring for long interconnects, while having an area overhead equivalent to 2 boundary scan cells only for each interconnect.
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