Monitor the Delay of Long Interconnect via Distributed TDC
碩士 === 國立清華大學 === 電機工程學系 === 103 === Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the del...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74197900782094685477 |